Espressif ESP32 Technical Reference Manual page 46

3 Reset and Clock
Name
SYSCON_PLL_TICK_CONF_REG
SYSCON_CK8M_TICK_CONF_REG
SYSCON_APLL_TICK_CONF_REG
Chip revision register
SYSCON_DATE_REG
3.4 Registers
The addresses in this section are relative to the SYSCON base address provided in Table
Mapping in Chapter 1 System and
31
0 0 0 0 0 0 0
SYSCON_PRE_DIV_CNT Configures the divider value of CPU_CLK when the source of CPU_CLK
is XTL_CLK or RC_FAST_CLK. The value range is 0x0 ~ 0x3FF. CPU_CLK = XTL_CLK ( or
RC_FAST_CLK) / (the value of this field +1). (R/W)
31
0 0 0 0 0 0 0
SYSCON_XTAL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is XTL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)
Espressif Systems
Description
Configures the divider value of REF_TICK
Configures the divider value of REF_TICK
Configures the divider value of REF_TICK
Chip revision register
Memory.
Register 3.1. SYSCON_SYSCLK_CONF_REG (0x0000)
0 0 0 0 0 0 0 0
Register 3.2. SYSCON_XTAL_TICK_CONF_REG (0x0004)
0 0 0 0 0 0 0 0
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10 9
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
46
Address
0x0008
0x000C
0x003C
0x007C
1-6 Peripheral Address
0x0
8 7
0 39
ESP32 TRM (Version 5.2)
Access
R/W
R/W
R/W
R/W
0
Reset
0
Reset