Espressif ESP32 Technical Reference Manual page 80

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
31
x x x x x x x
RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1 means
this GPIO pad is output. (R/W)
Register 4.39. RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010)
31
x x x x x x x
RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO)
Register 4.40. RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014)
31
x x x x x x x
RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO)
Espressif Systems
Register 4.38. RTCIO_RTC_GPIO_ENABLE_REG (0x000C)
x x x x x x x x
x x x x x x x x
x x x x x x x x
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14 13
x x x 0 0 0 0 0
14 13
x x x 0 0 0 0 0
14 13
x x x 0 0 0 0 0
80
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
0 Reset
0
0 Reset