Espressif ESP32 Technical Reference Manual page 341

12 I2S Controller (I2S)
31
I2S_LC_STATE1_REG Transmitter DMA channel status register. (RO)
31
0 0 0 0 0 0 0
I2S_LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout. (R/W)
I2S_LC_FIFO_TIMEOUT_SHIFT The bits are used to set the tick counter threshold. The tick counter
is reset when the counter value >= 88000/2
I2S_LC_FIFO_TIMEOUT When the value of FIFO hung counter is equal to this bit value, sending
data-timeout interrupt or receiving data-timeout interrupt will be triggered. (R/W)
Espressif Systems
Register 12.26. I2S_LC_STATE1_REG (0x0070)
0x000000000
Register 12.27. I2S_LC_HUNG_CONF_REG (0x0074)
0 0 0 0 0 0 0 0
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12 11 10
0 0 0 0 0 1 0 0
i2s_lc_fifo_timeout_shift
. (R/W)
341
8 7
0 0x010
ESP32 TRM (Version 5.2)
0
Reset
0
Reset