Espressif ESP32 Technical Reference Manual page 627

28 Process ID Controller (PID)
PIDCTRL_INTERRUPT_ENABLE_REG bit
Priority level
controlling interrupt identification
Level 1 1
Level 2 2
Level 3 3
Level 4 4
Level 5 5
Level 6 ( Debug 6
)
NMI 7
28.3.2 Information Recording
When PID Controller identifies an interrupt, it records three items of information in addition to switching PID to 0.
The recorded information includes the priority level of current interrupt, previous interrupt status of the system
and the previous process running on the CPU.
PID Controller records the priority level of the current interrupt in register PIDCTRL_LEVEL_REG. For details
please refer to Table 28-2.
Value
0
1
2
3
4
5
6
7
PID Controller also records in register
occurred. The bit width of register
status of the system before the interrupt indicated by the register occurred. The lowest three bits represent the
process running on the CPU before the interrupt indicated by the register occurred. For details please refer to
Table 28-3.
Espressif Systems
Table 28-1. Interrupt Vector Entry Address
Table 28-2. Configuration of PIDCTRL_LEVEL_REG
Priority level of the current interrupt
No interrupt
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
NMI
PIDCTRL_FROM_n_REG
PIDCTRL_FROM_n_REG
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Interrupt vector entry address
PIDCTRL_INTERRUPT_ADDR_1_REG
PIDCTRL_INTERRUPT_ADDR_2_REG
PIDCTRL_INTERRUPT_ADDR_3_REG
PIDCTRL_INTERRUPT_ADDR_4_REG
PIDCTRL_INTERRUPT_ADDR_5_REG
PIDCTRL_INTERRUPT_ADDR_6_REG
PIDCTRL_INTERRUPT_ADDR_7_REG
the status of the system before the interrupt
is 7. The highest four bits represent the interrupt
ESP32 TRM (Version 5.2)