Espressif ESP32 Technical Reference Manual page 75

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
31
0 0 0 0 0 0 0
GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W)
bit0: APP CPU interrupt enable;
bit1: APP CPU non-maskable interrupt enable;
bit2: PRO CPU interrupt enable;
bit3: PRO CPU non-maskable interrupt enable.
GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep.
(R/W)
GPIO_PINn_INT_TYPE Interrupt type selection: (R/W)
0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.
GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W)
Register 4.31. GPIO_FUNCy_IN_SEL_CFG_REG (y: 0-255) (0x130+0x4*y)
31
0 0 0 0 0 0 0
GPIO_SIGy_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal directly
to peripheral configured in the IO_MUX. (R/W)
GPIO_FUNCy_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W)
GPIO_FUNCy_IN_SEL Selection control for peripheral input y. A value of 0-39 selects which of the
40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30
for a constantly low input. (R/W)
Espressif Systems
Register 4.30. GPIO_PINn_REG (n: 0-39) (0x88+0x4*n)
18 17
0 0 0 0 0 0 0 x
0 0 0 0 0 0 0 0
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13 12 11 10 9
x x x x 0 0 x x
0 0 0 0 0 0 0 0
75
7 6 3 2 1
x x 0 0 0 0 x 0
8 7 6 5
0 x x x x x x x
ESP32 TRM (Version 5.2)
0
0 Reset
0
x Reset