Espressif ESP32 Technical Reference Manual page 329

12 I2S Controller (I2S)
12.8 Registers
The addresses in parenthesis besides register names are the register addresses relative to the I2S0/I2S1 base
addresses provided in Table
register addresses are listed in Section
31
0 0 0
I2S_FIFO_WR_REG Writes the data sent by I2S into FIFO. (WO)
31
0 0 0
I2S_FIFO_RD_REG Stores the data that I2S receives from FIFO. (RO)
Espressif Systems
1-6 Peripheral Address Mapping in Chapter
12.7 Register Summary.
Register 12.1. I2S_FIFO_WR_REG (0x0000)
0 0 0
Register 12.2. I2S_FIFO_RD_REG (0x0004)
0 0 0
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0 0 0
0 0 0
329
Memory. The absolute
0 0 0
0 0 0
ESP32 TRM (Version 5.2)
0
0
0
0