Espressif ESP32 Technical Reference Manual page 151

7 SPI Controller (SPI)
31
0 0 0 0 0 0 0
SPI_TX_CRC_REG Reserved.
31
0 0 0 0 0 0 0
SPI_ST The current state of the SPI state machine: (RO)
0: idle state
1: preparation state
2: send command state
3: send data state
4: read data state
5: write data state
6: wait state
7: done state
Espressif Systems
Register 7.23. SPI_TX_CRC_REG (0xC0)
0 0 0 0 0 0 0 0
Register 7.24. SPI_EXT2_REG (0xF8)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
151
0 0 0 0 0 0 0 0
3 2
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
0 Reset