Espressif ESP32 Technical Reference Manual page 514

18 Timer Group (TIMG)
18.4 Registers
The addresses in parenthesis besides register names are the register addresses relative to the TIMG base
address provided in Table
register addresses are listed in Section
31 30
0 1
TIMGn_Tx_EN When set, the timer
TIMGn_Tx_INCREASE When set, the timer
When cleared, the timer
TIMGn_Tx_AUTORELOAD When set, timer
TIMGn_Tx_DIVIDER Timer
TIMGn_Tx_EDGE_INT_EN When set, an alarm will generate an edge type interrupt. (R/W)
TIMGn_Tx_LEVEL_INT_EN When set, an alarm will generate a level type interrupt. (R/W)
TIMGn_Tx_ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an
alarm occurs. (R/W)
31
TIMGn_TxLO_REG After writing to TIMGn_TxUPDATE_REG, the low 32 bits of the time-base counter
of timer x can be read here. (RO)
31
TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter
of timer x can be read here. (RO)
Espressif Systems
1-6 Peripheral Address Mapping in Chapter
18.3 Register
Register 18.1. TIMGn_TxCONFIG_REG (x: 0-1) (0x0+0x24*x)
29 28
1
x time-base counter is enabled. (R/W)
x time-base counter will decrement. (R/W)
x
x clock (Tx_clk) prescale value. (R/W)
Register 18.2. TIMGn_TxLO_REG (x: 0-1) (0x4+0x24*x)
0x000000000
Register 18.3. TIMGn_TxHI_REG (x: 0-1) (0x8+0x24*x)
0x000000000
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1 System and
Summary.
0x00001
x time-base counter will increment every clock tick.
auto-reload at alarm is enabled. (R/W)
514
Memory. The absolute
13 12 11 10
0 0 0
Reset
ESP32 TRM (Version 5.2)
0
Reset
0
Reset