Espressif ESP32 Technical Reference Manual page 298

11 I2C Controller (I2C)
Figure 11-11 shows the Master reading data from a specified address in the Slave. This mode can be enabled
by setting I2C_FIFO_ADDR_CFG_EN and preparing the data to be read by the master in the Slave RAM block.
Subsequently, the address of the Slave and the address of the specified register (that is, M) have to be deter-
mined by the master. Finally, the I2C_TRANS_START bit must be set in the Master to initiate the read operation,
following which the Slave will fetch N bytes of data from RAM and send them to the Master.
Figure 11-11. Master Reads N Bytes of Data from addrM in Slave with 7-bit Address
Figure 11-12 shows the Master reading N+M bytes of data in three segments from the Slave. The first segment
shows the configuration of the cmd and the preparation of data in the Slave RAM. When the I2C_TRANS_START
bit is enabled, the Master starts the operation. The Master will refresh the cmd after executing the END com-
mand. It will clear the I2C_END_DETECT_INT interrupt, set the I2C_TRANS_START bit and resume the transac-
tion. To stop the transaction, the Master will configure the cmd, as the third segment shows, after detecting
the I2C_END_DETECT_INT interrupt. After setting the I2C_TRANS_START bit, Master will send a STOP bit to stop
the transaction.
Espressif Systems
Figure 11-10. Master Reads from Slave with 10-bit Address
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298 ESP32 TRM (Version 5.2)