Espressif ESP32 Technical Reference Manual page 592

23 SHA Accelerator (SHA)
23.5 Registers
The addresses in parenthesis besides register names are the register addresses relative to the SHA base address
provided in Table 1-6 Peripheral Address Mapping in Chapter
addresses are listed in Section
31
SHA_TEXT_n_REG (n: 0-31) SHA Message block and hash result register. (R/W)
31
SHA_SHA1_START Write 1 to start an SHA-1 operation on the first message block. (WO)
31
SHA_SHA1_CONTINUE Write 1 to continue the SHA-1 operation with subsequent blocks. (WO)
31
SHA_SHA1_LOAD Write 1 to finish the SHA-1 operation to calculate the final message hash. (WO)
Espressif Systems
23.4 Register Summary.
Register 23.1. SHA_TEXT_n_REG (n: 0-31) (0x0+4*n)
0x000000000
Register 23.2. SHA_SHA1_START_REG (0x080)
0x00000000
Register 23.3. SHA_SHA1_CONTINUE_REG (0x084)
0x00000000
Register 23.4. SHA_SHA1_LOAD_REG (0x088)
0x00000000
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1 System and
592
Memory. The absolute register
0
1 0
0
1 0
0
1 0
0
ESP32 TRM (Version 5.2)
Reset
Reset
Reset
Reset