Espressif ESP32 Technical Reference Manual page 126

6 DMA Controller (DMA)
6.6 I2S DMA Interface
The ESP32 integrates two I2S modules, I2S0 and I2S1, each of which is powered by a DMA channel. The
REG_I2S_DSCR_EN bit in I2S_FIFO_CONF_REG is used for enabling the DMA operation. ESP32 I2S DMA
uses the standard linked-list descriptor to configure DMA operations for data transfer. Burst transfer is sup-
ported. However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.
REG_I2S_RX_EOF_NUM[31:0] bit in I2S_RXEOF_NUM_REG is used for configuring the data size of a single trans-
fer operation, in multiples of one word.
I2S_OUTLINK_START bit in I2S_OUT_LINK_REG and I2S_INLINK_START bit in I2S_IN_LINK_REG are used for en-
abling the DMA Engine and are self-cleared by hardware. When I2S_OUTLINK_START is set to 1, the DMA Engine
starts processing the outbound linked-list descriptor and gets prepared to send data. When I2S_INLINK_START
is set to 1, the DMA Engine starts processing the inbound linked-list descriptor and gets prepared to receive
data.
Software should configure the I2S DMA as follows:
1. Configure I2S-controller-related registers;
2. Reset the DMA state machine and FIFO parameters;
3. Configure DMA-related registers for operation;
4. In I2S master mode, set I2S_TX_START bit or I2S_RX_START bit to initiate an I2S operation;
In I2S slave mode, set I2S_TX_START bit or I2S_RX_START bit and wait for data transfer to be initiated by
the host device.
For more information on I2S DMA interrupts, please see Section DMA Interrupts, in Chapter I2S.
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