Espressif ESP32 Technical Reference Manual page 192

8 SDIO Slave Controller
31
0 0 0 0 0 0 0
SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)
SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)
31 28 27 26
0 0 0 0 0 0 0
SLCHOST_HSPEED_CON_EN Set this bit and HINF_HIGHSPEED_ENABLE, then set the EHS (Enable
High-Speed) bit in CCCR at the Host side to output the corresponding signal at the rising clock
edge. (R/W)
SLCHOST_FRC_POS_SAMP Set this bit to sample the corresponding signal at the rising clock edge.
(R/W)
SLCHOST_FRC_NEG_SAMP Set this bit to sample the corresponding signal at the falling clock edge.
(R/W)
SLCHOST_FRC_SDIO20 Set this bit to output the corresponding signal at the rising clock edge.
(R/W)
SLCHOST_FRC_SDIO11 Set this bit to output the corresponding signal at the falling clock edge.
(R/W)
8.7 HINF Registers
The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave
base address (0x3FF4_B000) provided in Table
Memory. The absolute register addresses are listed in Section
Espressif Systems
Register 8.34. SLCHOST_CONF_W7_REG (0x8C)
24 23
0 0x000
Register 8.35. SLCHOST_CONF_REG (0x1F0)
20 19
0 0 0 0 0 0 0 0
1-6
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16 15
0 0 0 0 0 0 0
15 14 10 9
0 0 0 0 0 0 0 0
Peripheral Address Mapping in Chapter
8.4 Register
192
8 7
0 0x000
5 4
0 0 0 0 0 0 0 0
1 System and
Summary.
ESP32 TRM (Version 5.2)
0
Reset
0
0 Reset