Espressif ESP32 Technical Reference Manual page 238

10 Ethernet Media Access Controller (MAC)
10.6.3 Station Management Agent (SMA) Interface
As Figure 10-4 shows, the MAC uses MDC and MDIO signals to transfer control and data information to the
PHY. The maximum clock frequency is 2.5 MHz. The clock is generated from the application clock by a clock
divider. The PHY transmits register data during a write/read operation through the MDIO. This signal is driven
synchronously to the MDC clock.
Please refer to Register Summary
10.6.4 RMII Timing
This section describes the RMII timing specifications.
Espressif Systems
Figure 10-6. RMII Clock
for details about the EMII Address Register and the EMII Data Register.
Figure 10-7. RMII Timing - Receiving Data
Table 10-3. Timing Parameters - Receiving Data
Timing Parameters Description
t Clock cycle
CY C
t Setup time
SU
t Hold time
H
t Input delay
ID
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Min Typ Max
20 20 20
4 – –
1 – –
3 5 8
238
Unit
ns
ns
ns
ns
ESP32 TRM (Version 5.2)