Espressif ESP32 Technical Reference Manual page 239

10 Ethernet Media Access Controller (MAC)
10.7 Ethernet DMA Features
The DMA has independent Transmit and Receive engines, and a CSR (Control and Status Registers) space. The
Transmit engine transfers data from the system memory to the device port (MTL), while the Receive engine
transmits data from the device port to the system memory. The controller uses descriptors to efficiently move
data from source to destination with minimal Host CPU intervention. The DMA is designed for packet-oriented
data transmission, such as frames in Ethernet. The controller can be programmed to interrupt the Host CPU for
normal situations, such as the completion of frame transmission or reception, or when errors occur.
10.8 Linked List Descriptors
This section shows the structure of the linked lists and the descriptors. Every linked list consists of eight
words.
10.8.1 Transmit Descriptors
The structure of the transmitter linked lists is shown in Figure 10-9. Table
of the linked lists.
31
TDES0 Ctrl[30:26]
Ctrl
TDES1
[31:29]
TDES2
TDES3
TDES4
TDES5
TDES6
TDES7
Espressif Systems
Figure 10-8. RMII Timing – Transmitting Data
Table 10-4. Timing Parameters – Transmitting Data
Timing Parameters Description
t Clock cycle
CY C
t Setup time
SU
t Hold time
H
t Output delay
OD
Ctrl[24:18]
Reserved
Next Descriptor Address[31:0]
Figure 10-9. Transmit Descriptor
Submit Documentation Feedback
Min Typ
20 20
4 –
1 –
6 9
10-5
Status[16:7]
Transmit Buffer Size[12:0]
Buffer Address [31:0]
Reserved
Reserved
Reserved
Reserved
239
Max Unit
20 ns
– ns
– ns
12 ns
to Table 10-8 show the description
Ctrl/status Status
[6:3] [2:0]
ESP32 TRM (Version 5.2)
0