Espressif ESP32 Technical Reference Manual page 287

10 Ethernet Media Access Controller (MAC)
31 25
0 0 0 0 0 0 0
EMAC_OSC_CLK_SEL Ethernet work using external PHY output clock or not for RMII CLK, when
using RMII PHY. When this bit is set to 1, external PHY CLK is used. When this bit is set to 0, APLL
CLK is used. (R/W)
EMAC_OSC_H_DIV_NUM_100M RMII/MII
EMAC_EX_CLKOUT_CONF clock divider's speed is 100M. (R/W)
EMAC_OSC_DIV_NUM_100M RMII/MII
EMAC_EX_CLKOUT_CONF clock divider's speed is 100M. (R/W)
EMAC_OSC_H_DIV_NUM_10M RMII/MII
EMAC_EX_CLKOUT_CONF clock divider's speed is 10M. (R/W)
EMAC_OSC_DIV_NUM_10M RMII/MII
EMAC_EX_CLKOUT_CONF clock divider's speed is 10M. (R/W)
31
0 0 0 0 0 0 0
EMAC_MII_CLK_RX_EN Enable Ethernet RX CLK. (R/W)
EMAC_MII_CLK_TX_EN Enable Ethernet TX CLK. (R/W)
EMAC_INT_OSC_EN Using internal APLL CLK in RMII PHY mode. (R/W)
EMAC_EXT_OSC_EN Using external APLL CLK in RMII PHY mode. (R/W)
Espressif Systems
Register 10.45. EMAC_EX_OSCCLK_CONF_REG (0x0804)
24 23 18 17
0 0
Register 10.46. EMAC_EX_CLK_CTRL_REG (0x0808)
0 0 0 0 0 0 0 0
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12 11
1 9
half-integer divider,
whole-integer divider,
half-integer divider,
whole-integer divider,
0 0 0 0 0 0 0 0
287
6 5
19
when register
when register
when register
when register
6 5 4 3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
Reset
0
0
Reset