Espressif ESP32 Technical Reference Manual page 303

11 I2C Controller (I2C)
31 30 28 27 26
0 0 0 0 0 0 0
I2C_SCL_STATE_LAST This field indicates the states of the state machine used to produce SCL.
(RO)
0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
I2C_SCL_MAIN_STATE_LAST This field indicates the states of the I2C module state machine. (RO)
0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK
I2C_TXFIFO_CNT This field stores the amount of received data in RAM. (RO)
I2C_RXFIFO_CNT This field represents the amount of data needed to be sent. (RO)
I2C_BYTE_TRANS This field changes to 1 when one byte is transferred. (RO)
I2C_SLAVE_ADDRESSED When configured as an I2C Slave, and the address sent by the master is
equal to the address of the slave, then this bit will be of high level. (RO)
I2C_BUS_BUSY 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. (RO)
I2C_ARB_LOST When the I2C controller loses control of SCL line, this register changes to 1. (RO)
I2C_TIME_OUT When the I2C controller takes more than I2C_TIME_OUT clocks to receive a data
bit, this field changes to 1. (RO)
I2C_SLAVE_RW When in slave mode, 1: master reads from slave; 0: master writes to slave. (RO)
I2C_ACK_REC This register stores the value of the received ACK bit. (RO)
31
0 0 0 0 0 0 0
I2C_TIME_OUT_REG This register is used to configure the timeout for receiving a data bit in APB
clock cycles. (R/W)
Espressif Systems
Register 11.3. I2C_SR_REG (0x0008)
24 23 18 17
0 0 0 0 0 0 0 0
Register 11.4. I2C_TO_REG (0x000c)
20 19
0 0 0 0 0 0 0 0
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14 13
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
303
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0 Reset
0
0 Reset