Espressif ESP32 Technical Reference Manual page 42

3 Reset and Clock
3.2.2 Clock Source
The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source.
Specifically, the clock sources available are:
• High Speed Clocks
– PLL_CLK is an internal PLL clock with a frequency of 320 MHz or 480 MHz.
– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.
• Low Power Clocks
– XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz.
– RC_FAST_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.
– RC_FAST_DIV_CLK is divided from RC_FAST_CLK. Its frequency is (RC_FAST_CLK / 256). With the
default RC_FAST_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.
– RC_SLOW_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.
• Audio Clock
– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.
3.2.3 CPU Clock
As Figure 3-2 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 240
MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce
power consumption.
The CPU_CLK clock source is determined by the
RC_FAST_CLK, and XTL_CLK can be set as the CPU_CLK source; see Table
Clock Source
XTL_CLK
PLL_CLK (320 MHz)
PLL_CLK (320 MHz)
PLL_CLK (480 MHz)
RC_FAST_CLK
APLL_CLK
Espressif Systems
Table 3-2. CPU_CLK Source
RTC_CNTL_SOC_CLK_SEL
0
1
2
3
Table 3-3. CPU_CLK Derivation
*SEL_0 *SEL_1 CPU Clock Frequency
0 - CPU_CLK = XTL_CLK / (SYSCON_PRE_DIV_CNT+1)
CPU_CLK = PLL_CLK / 4
1 0
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
1 1
CPU_CLK frequency is 160 MHz
CPU_CLK = PLL_CLK / 2
1 2
CPU_CLK frequency is 240 MHz
2 - CPU_CLK = RC_FAST_CLK / (SYSCON_PRE_DIV_CNT+1)
3 0 CPU_CLK = APLL_CLK / 4
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RTC_CNTL_SOC_CLK_SEL
Value Clock Source
XTL_CLK
PLL_CLK
RC_FAST_CLK
APLL_CLK
42
register. PLL_CLK, APLL_CLK,
3-2 and 3-3.
ESP32 TRM (Version 5.2)