Espressif ESP32 Technical Reference Manual page 325

12 I2S Controller (I2S)
I2SnI_Data_in, there are other signals, such as I2Sn_H_SYNC, I2Sn_V_SYNC and I2Sn_H_ENABLE.
The PCLK in the Camera module connects to I2SnI_WS_in in the I2S module, as Figure 12-16 shows.
Figure 12-16. Camera Slave Receiving Mode
When I2S is in the camera slave receiving mode, and when I2Sn_H_SYNC, I2S_V_SYNC and I2S_H_REF are
held high, the master starts transmitting data, that is,
transmission_start = (I2Sn_H_SY N C == 1)&&(I2Sn_V _SY N C == 1)&&(I2Sn_H_EN ABLE == 1)
Thus, during data transmission, these three signals should be kept at a high level. For example, if the I2Sn_V_SYNC
signal of a camera is at low level during data transmission, it will be inverted when routed to the I2S module.
ESP32 supports signal inversion through the GPIO matrix. For details, please refer to the chapter about IO_MUX
and the GPIO Matrix.
In order to make I2S work in camera mode, the I2S_LCD_EN bit and the I2S_CAMERA_EN bit of register
I2S_CONF2
_REG are set to 1, the I2S_RX_SLAVE_MOD bit of register I2S_CONF_REG is set to 1, the I2S_RX_MSB_RIGHT
bit and the I2S_RX_RIGHT_FIRST bit of I2S_CONF_REG are set to 0. Thus, I2S works in the LCD slave receiving
mode. At the same time, in order to use the correct mode to receive data, both the I2S_RX_CHAN_MOD[2:0]
bit of register I2S_CONF_CHAN_REG and the I2S_RX_FIFO_MOD[2:0] bit of register I2S_FIFO_CONF_REG are
set to 1.
12.5.3 ADC/DAC mode
In LCD mode, ESP32's ADC and DAC can receive data. When the I2S0 module connects to the on-chip ADC,
the I2S0 module should be set to master receiving mode. Figure 12-17 shows the signal connection between
the I2S0 module and the ADC.
Figure 12-17. ADC Interface of I2S0
Firstly, the I2S_LCD_EN bit of register I2S_CONF2_REG is set to 1, and the I2S_RX_SLAVE_MOD bit of register
Espressif Systems 325 ESP32 TRM (Version 5.2)
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