Espressif ESP32 Technical Reference Manual page 143

7 SPI Controller (SPI)
31 30 29 28 27 26 25
1 0 0 0 0 0 0
SPI_USR_COMMAND This bit enables the command phase of an SPI operation in SPI half-duplex
mode and QSPI mode. (R/W)
SPI_USR_ADDR This bit enables the address phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_DUMMY This bit enables the dummy phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_MISO This bit enables the read-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_MOSI This bit enables the write-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_DUMMY_IDLE The SPI clock signal is disabled in the dummy phase when the bit is set in
SPI half-duplex mode and QSPI mode. (R/W)
SPI_USR_MOSI_HIGHPART If set, MOSI data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)
SPI_USR_MISO_HIGHPART If set, MISO data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)
SPI_SIO Set this bit to enable three-line half-duplex communication. (R/W)
SPI_FWRITE_QIO Reserved.
SPI_FWRITE_DIO Reserved.
SPI_FWRITE_QUAD Reserved.
SPI_FWRITE_DUAL Reserved.
SPI_WR_BYTE_ORDER This bit determines the byte order of the command, address and data in
transmitted signal. 1: big-endian; 0: little-endian. (R/W)
SPI_RD_BYTE_ORDER This bit determines the byte order of received data in transmitted signal. 1:
big-endian; 0: little_endian. (R/W)
SPI_CK_OUT_EDGE This bit, combined with SPI_MOSI_DELAY_MODE, sets the MOSI signal delay
mode. It is only valid in master mode. (R/W)
SPI_CK_I_EDGE In slave mode, the bit is the same as SPI_CK_OUT_EDGE in master mode. It is
combined with SPI_MISO_DELAY_MODE. It is only valid in slave mode. (R/W)
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Espressif Systems
Register 7.8. SPI_USER_REG (0x1C)
24 23 17
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
143
8 7 6 5 4 3 1
0 0 1 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset