Espressif ESP32 Technical Reference Manual page 129

7 SPI Controller (SPI)
Table 7-2. Command Definitions Supported by GP-SPI Slave in Half-duplex Mode
Command Description
0x1 Received by slave; writes data sent by the master into the slave status register via MOSI.
0x2 Received by slave; writes data sent by the master into the slave data buffer via MOSI.
0x3 Sent by slave; sends data in the slave buffer to master via MISO.
0x4 Sent by slave; sends data in the slave status register to master via MISO.
Writes master data on MOSI into data buffer and then sends the date in the slave data buffer
0x6
to MISO.
7.3.1 GP-SPI Four-line Full-duplex Communication
When configured to four-line full-duplex mode, the ESP32 SPI can act as either a master or a slave. The length
of received and sent data needs to be set by configuring the SPI_MISO_DLEN_REG, SPI_MOSI_DLEN_REG
registers for master mode as well as SPI_SLV_RDBUF_DLEN_REG, SPI_SLV_WRBUF_DLEN_REG registers for
slave mode. The SPI_DOUTDIN bit and SPI_USR_MOSI bit in register SPI_USER_REG should be configured to
enable this communication mode. The SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize
a data transfer.
7.3.2 GP-SPI Four-line Half-duplex Communication
When configured to four-line half-duplex mode, the ESP32 SPI can act as either a master or a slave. In this
mode, the SPI communication supports flexible communication format as: command + address + dummy phase
+ received and/or sent data. The format is specified as follows:
1. command: length of 0~16 bits; Master Out Slave In (MOSI).
2. address: length of 0~32/64 bits; Master Out Slave In (MOSI).
3. dummy phase: length of 0~256 SPI clocks.
4. received and/or sent data: length of 0~512 bits (64 bytes); Master Out Slave In (MOSI) or Master In Slave
Out (MISO).
The address length is up to 32 bits in GP-SPI master mode and 64 bits in QSPI master mode. The command
phase, address phase, dummy phase and received/sent data phase are controlled by bits SPI_USR_COMMAND,
SPI_USR_ADDR, SPI_USR_DUMMY, and SPI_USR_MISO/SPI_USR_MOSI respectively in register SPI_USER_REG.
A certain phase is enabled only when its corresponding control bit is set to 1. Details can be found in
description. When SPI works as a master, the register can be configured by software as required to determine
whether or not to enable a certain phase.
When SPI works as a slave, the communication format must contain command, address, received and/or sent
data, among which the command has several options listed in Table 7-2. During data transmission or reception,
the CS signal should keep logic level low. If the CS signal is pulled up during transmission, the internal state of
the slave will be reset.
The master can write the slave status register SPI_SLV_WR_STATUS_REG, and decide whether to read data from
register SPI_SLV_WR_STATUS_REG or register SPI_RD_STATUS_REG via the SPI_SLV_STATUS_READBACK bit in
register SPI_SLAVE1_REG. The SPI master can maintain communication with the slave by reading and writing
slave status register, thus realizing complex communication with ease.
The length of received and sent data is controlled by SPI_MISO_DLEN_REG and SPI_MOSI_DLEN_REG in master
mode, as well as SPI_SLV_RDBUF_DLEN_REG and SPI_SLV_WRBUF_DLEN_REG in slave mode. A reception or
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ESP32 TRM (Version 5.2)