Espressif ESP32 Technical Reference Manual page 340

12 I2S Controller (I2S)
31
0 0 0 0 0 0 0
I2S_CHECK_OWNER Set this bit to check the owner bit by hardware. (R/W)
I2S_OUT_DATA_BURST_EN Transmitter data transfer mode configuration bit. (R/W)
1: Transmit data in burst mode;
0: Transmit data in byte mode.
I2S_INDSCR_BURST_EN DMA inlink descriptor transfer mode configuration bit. (R/W)
1: Transfer inlink descriptor in burst mode;
0: Transfer inlink descriptor in byte mode.
I2S_OUTDSCR_BURST_EN DMA outlink descriptor transfer mode configuration bit. (R/W)
1: Transfer outlink descriptor in burst mode;
0: Transfer outlink descriptor in byte mode.
I2S_OUT_EOF_MODE DMA
1: When DMA has popped all data from the FIFO;
0: When AHB has pushed all data to the FIFO.
I2S_OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx
buffer has been transmitted. (R/W)
I2S_OUT_LOOP_TEST Set this bit to loop test outlink. (R/W)
I2S_IN_LOOP_TEST Set this bit to loop test inlink. (R/W)
I2S_AHBM_RST Set this bit to reset AHB interface of DMA. (R/W)
I2S_AHBM_FIFO_RST Set this bit to reset AHB interface cmdFIFO of DMA. (R/W)
I2S_OUT_RST Set this bit to reset out DMA FSM. (R/W)
I2S_IN_RST Set this bit to reset in DMA FSM. (R/W)
31
I2S_LC_STATE0_REG Receiver DMA channel status register. (RO)
Espressif Systems
Register 12.24. I2S_LC_CONF_REG (0x0060)
0 0 0 0 0 0 0 0
I2S_OUT_EOF_INT
Register 12.25. I2S_LC_STATE0_REG (0x006c)
0x000000000
Submit Documentation Feedback
13 12 11 10 9 8
0 0 0 0 0 0 0 1
generation mode. (R/W)
340
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0
ESP32 TRM (Version 5.2)
Reset
Reset