Espressif ESP32 Technical Reference Manual page 268

10 Ethernet Media Access Controller (MAC)
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DAIF When this bit is set, the Address Check block operates in inverse filtering mode for the DA
address comparison for both unicast and multicast frames. When reset, normal filtering of frames
is performed. (R/W)
PMODE When this bit is set, the Address Filter module passes all incoming frames irrespective of
the destination or source address. The SA or DA Filter Fails status bits of the Receive Status
Word are always cleared when PR(PRT_RATIO) is set. (R/W)
31
0 0 0 0 0 0 0
MIIDEV This field indicates which of the 32 possible PHY devices are being accessed. (R/W)
MIIREG This field selects the desired MII register in the selected PHY device. (R/W)
MIICSRCLK This field selects the APB clock frequency. It has the following two values. Other values
are reserved.
• 4'b0000: The APB clock frequency is 80 MHz. The MDC clock frequency is APB_CLK/42.
• 4'b0011: The APB clock frequency is 40 MHz. The MDC clock frequency is APB_CLK/26.
(R/W)
MIIWRITE When set, this field indicates to the PHY that this is a Write operation using MII_DATA. If
this field is not set, it indicates that this is a Read operation, that is, placing the data in MII_DATA.
(R/W)
MIIBUSY This field is used in combination with
Before writing to
To read or write to
MII_DATA should be kept valid (data remains unchanged) when it is accessed until this field is
cleared by hardware (the MAC).
Note that ESP32 MAC does not receive ACK from PHY during a read or write access to
and MII_DATA. (R/WS/SC)
Espressif Systems
Register 10.16. EMACFF_REG (0x1004)
Register 10.17. EMACGMIIADDR_REG (0x1010)
0 0 0 0 0 0 0 0
MIIREG and MII_DATA, this field should read logic 0 (idle state by default).
MIIREG and MII_DATA, software (the user) should set this field to 1.
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16 15 11 10
0 0x00 0x00
MIIREG and MII_DATA.
268
6 5 2 1 0
0x00 0 0
Reset
MIIREG
ESP32 TRM (Version 5.2)