Espressif ESP32 Technical Reference Manual page 702

31 Low-Power Management (RTC_CNTL)
31.4 Register Summary
Notes:
• The registers listed below have been grouped according to their functionality. This particular grouping
does not reflect the exact sequential order in which they are stored in memory.
• The base address for registers is 0x60008000 when accessed by AHB, and 0x3FF48000 when accessed
by DPORT bus.
Name
RTC option register
RTC_CNTL_OPTIONS0_REG
Control and configuration of RTC timer registers
RTC_CNTL_SLP_TIMER0_REG
RTC_CNTL_SLP_TIMER1_REG
RTC_CNTL_TIME_UPDATE_REG
RTC_CNTL_TIME0_REG
RTC_CNTL_TIME1_REG
RTC_CNTL_STATE0_REG
RTC_CNTL_TIMER1_REG
RTC_CNTL_TIMER2_REG
RTC_CNTL_TIMER5_REG
Espressif Systems
Figure 31-11. ESP32 Boot Flow
Description
Configure RTC options
RTC sleep timer
RTC sleep timer, alarm and control
Update control of RTC timer
RTC timer low 32 bits
RTC timer high 16 bits
RTC sleep, SDIO and ULP control
CPU stall enable
Slow clock and touch controller config-
uration
Minimal sleep cycles in slow clock
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Address Access
0x3FF48000 R/W
0x3FF48004 R/W
0x3FF48008 R/W
0x3FF4800C RO
0x3FF48010 RO
0x3FF48014 RO
0x3FF48018 R/W
0x3FF4801C R/W
0x3FF48020 R/W
0x3FF4802C R/W
ESP32 TRM (Version 5.2)