Espressif ESP32 Technical Reference Manual page 498

16 Motor Control PWM (PWM)
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INT_FAULT1_INT_ST The masked status bit for the interrupt triggered when event_f1 starts. (RO)
INT_FAULT0_INT_ST The masked status bit for the interrupt triggered when event_f0 starts. (RO)
INT_TIMER2_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 2 TEP
event. (RO)
INT_TIMER1_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 1 TEP
event. (RO)
INT_TIMER0_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 0 TEP
event. (RO)
INT_TIMER2_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 2 TEZ
event. (RO)
INT_TIMER1_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 1 TEZ
event. (RO)
INT_TIMER0_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 0 TEZ
event. (RO)
INT_TIMER2_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 2 stops.
(RO)
INT_TIMER1_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 1 stops.
(RO)
INT_TIMER0_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 0 stops.
(RO)
Espressif Systems
Register 16.71. INT_ST_PWM_REG (0x0118)
498
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ESP32 TRM (Version 5.2)