Espressif ESP32 Technical Reference Manual page 554

21 Two-wire Automotive Interface (TWAI)
Segment Description
PBS2 PBS2 (Phase Buffer Segment 2) can be 1 to 8 Time Quanta long. PBS2 is meant to
compensate for the information processing time of nodes. PBS2 can also be short-
ened for synchronization purposes.
21.3.4.2 Hard Synchronization and Resynchronization
Due to clock skew and jitter, the bit timing of nodes on the same bus may become out of phase. Therefore, a
bit edge may come before or after the SS. To ensure that the internal bit timing clocks of each node are kept in
phase, TWAI has various methods of synchronization. The Phase Error "e" is measured in the number of Time
Quanta and relative to the SS.
• A positive Phase Error (e > 0) is when the edge lies after the SS and before the Sample Point (i.e., the
edge is late).
• A negative Phase Error (e < 0) is when the edge lies after the Sample Point of the previous bit and before
SS (i.e., the edge is early).
To correct for Phase Errors, there are two forms of synchronization, known as Hard Synchronization and Resyn-
chronization. Hard Synchronization and Resynchronization obey the following rules.
• Only one synchronization may occur in a single bit time.
• Synchronizations only occurs on Recessive to Dominant edges.
Hard Synchronization
Hard Synchronization occurs on the Recessive to Dominant edges during Bus Idle (i.e., the SOF bit). All nodes
will restart their internal bit timings such that the Recessive to Dominant edge lies within the SS of the restarted
bit timing.
Resynchronization
Resynchronization occurs on Recessive to Dominant edges not during Bus Idle. If the edge has a positive
Phase Error (e > 0), PBS1 is lengthened by a certain number of Time Quanta. If the edge has a negative Phase
Error (e < 0), PBS2 will be shortened by a certain number of Time Quanta.
The number of Time Quanta to lengthen or shorten depends on the magnitude of the Phase Error, and is also
limited by the Synchronization Jump Width (SJW) value which is a programmable.
• When the magnitude of the Phase Error is less than or equal to the SJW, PBS1/PBS2 are lengthened/shortened
by e number of Time Quanta. This has a same effect as Hard Synchronization.
• When the magnitude of the Phase Error is greater to the SJW, PBS1/PBS2 are lengthened/shortened by
the SJW number of Time Quanta. This means it may take multiple bits of synchronization before the Phase
Error is entirely corrected.
21.4 Architectural Overview
The ESP32 contains a TWAI Controller. Figure
21.4.1 Registers Block
The ESP32 CPU accesses peripherals as 32-bit aligned words. However, the majority of registers in the TWAI
controller only contain useful data at the least significant byte (bits [7:0]). Therefore, in these registers, bits
[31:8] are ignored on writes, and return 0 on reads.
Espressif Systems
21-6 shows the major functional blocks of the TWAI Controller.
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