Espressif ESP32 Technical Reference Manual page 502

17 Pulse Count Controller (PCNT)
is a 16-bit signed up/down counter. Its value can be read by software directly, but is also monitored by a set of
comparators which can trigger an interrupt.
17.2.2 Counter Channel Inputs
As stated before, the two inputs of a channel can affect the pulse counter in various ways. The specifics of this
behaviour are set by LCTRL_MODE and HCTRL_MODE in this case when the control signal is low or high, respec-
tively, and POS_MODE and NEG_MODE for positive and negative edges of the input signal. Setting POS_MODE
and NEG_MODE to 1 will increase the counter when an edge is detected, setting them to 2 will decrease the
counter and setting at any other value will neutralize the effect of the edge on the counter. LCTR_MODE and
HCTR_MODE modify this behaviour, when the control input has the corresponding low or high value: 0 does
not modify the NEG_MODE and POS_MODE behaviour, 1 inverts it (setting POS_MODE/NEG_MODE to increase
the counter should now decrease the counter and vice versa) and any other value disables counter effects for
that signal level.
To summarize, a few examples have been considered. In this table, the effect on the counter for a rising edge
is shown for both a low and a high control signal, as well as various other configuration options. For clarity, a
short description in brackets is added after the values. Note: x denotes 'do not care'.
POS_ MODE LCTRL_ MODE
1 (inc) 0 (-)
2 (dec) 0 (-)
0 (-) x
1 (inc) 0 (-)
1 (inc) 1 (inv)
2 (dec) 0 (-)
1 (inc) 0 (-)
1 (inc) 2 (dis)
This table is also valid for negative edges (sig h→l) on substituting NEG_MODE for POS_MODE.
Each pulse counter unit also features a filter on each of the four inputs, adding the option to ignore short
glitches in the signals. If a
is enabled, any pulses shorter than
and will have no effect on the counter. With the filter disabled, in theory infinitely small glitches could possibly
trigger pulse counter action. However, in practice the signal inputs are sampled on APB_CLK edges and even
with the filter disabled, pulse widths lasting shorter than one APB_CLK cycle may be missed.
Apart from the input channels, software also has some control over the counter. In particular, the counter value
can be frozen to the current value by configuring PCNT_CNT_PAUSE_Un. It can also be reset to 0 by configuring
PCNT_PLUS_CNT_RST_Un.
17.2.3 Watchpoints
The pulse counters have five watchpoints that share one interrupt. Interrupt generation can be enabled or
disabled for each individual watchpoint. The watchpoints are:
• Maximum count value: Triggered when PULSE_CNT >= PCNT_CNT_H_LIM_Un. Additionally, this will reset
the counter to 0. PCNT_CNT_H_LIM_Un
• Minimum count value: Triggered when PULSE_CNT <= PCNT_CNT_L_LIM_Un. Additionally, this will reset
Espressif Systems
HCTRL_ MODE
0 (-)
0 (-)
x
1 (inv)
0 (-)
1 (inv)
2 (dis)
0 (-)
PCNT_FILTER_EN_Un can be set to filter the four input signals of the unit. If this filter
REG_FILTER_THRES_Un
should be a positive number.
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sig l→h when ctrl=0
Inc ctr
Dec ctr
No action
Inc ctr
Dec ctr
Dec ctr
Inc ctr
No action
number of APB_CLK clock cycles will be filtered out
502
sig l→h when ctrl=1
Inc ctr
Dec ctr
No action
Dec ctr
Inc ctr
Inc ctr
No action
Inc ctr
ESP32 TRM (Version 5.2)