Espressif ESP32 Technical Reference Manual page 78

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
Register 4.34. IO_MUX_x_REG (x: GPIO0-GPIO39) (0x10+4*x)
31
0 0 0 0 0 0 0
MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1,
etc. (R/W)
FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength.
For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table
"Notes on ESP32 Pin Lists", in
FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. (R/W)
FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO
pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-
down circuitry, therefore, their FUN_WPU is always 0. (R/W)
FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down dis-
abled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal
pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. (R/W)
MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds
with a higher strength. (R/W)
MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. (R/W)
MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal
pull-up disabled. (R/W)
MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: in-
ternal pull-down disabled. (R/W)
SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. (R/W)
MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W)
4.13.3 RTC IO MUX Registers
The addresses in parenthesis besides register names are the register addresses relative to (the RTC base ad-
dress + 0x0400). The RTC base address is provided in Table
System and Memory. The absolute register addresses are listed in Section
mary.
Espressif Systems
0 0 0 0 0 0 0 0
ESP32 Datasheet. (R/W)
Submit Documentation Feedback
15 14 12 11 10 9
0 0 0x0 0x2 0
1-6 Peripheral Address Mapping in Chapter
78
8 7 6 5 4 3 2 1
0 0 0x0 0 0 0 0
4.12.3 RTC IO MUX Register Sum-
ESP32 TRM (Version 5.2)
0
0
Reset
1