Espressif ESP32 Technical Reference Manual page 131

7 SPI Controller (SPI)
Table 7-3. Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master
Registers
SPI_CK_IDLE_EDGE
SPI_CK_OUT_EDGE
SPI_MISO_DELAY_MODE
SPI_MISO_DELAY_NUM
SPI_MOSI_DELAY_MODE
SPI_MOSI_DELAY_NUM
7.4 GP-SPI Clock Control
The maximum output clock frequency of ESP32 GP-SPI master is f
quency of the ESP32 GP-SPI slave is f
division.
SPI_CLKCNT_N and SPI_CLKDIV_PRE are two bits of register SPI_CLOCK_REG (Please refer to
scription for details). SPI_CLKCNT_H = ⌊
bit in register SPI_CLOCK_REG is set to 1, and the other bits are set to 0, SPI output clock frequency is
. For other clock frequencies, SPI_CLK_EQU_SYSCLK needs to be 0. In slave mode, SPI_CLKCNT_N,
f
apb
SPI_CLKCNT_L, SPI_CLKCNT_H and SPI_CLKDIV_PRE should all be 0.
7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA)
The clock polarity and clock phase of ESP32 SPI are controlled by SPI_CK_IDLE_EDGE bit in register SPI_PIN_REG,
SPI_CK_OUT_EDGE bit and SPI_CK_I_EDGE bit in register SPI_USER_REG, as well as SPI_MISO_DELAY_MODE[1:0]
bit, SPI_MISO_DELAY_NUM[2:0] bit, SPI_MOSI_DELAY_MODE[1:0] bit, SPI_MOSI_DELAY_MUM[2:0] bit in reg-
ister SPI_CTRL2_REG. Table
register values for ESP32 SPI master and slave, respectively. Note that for mode0 and mode2 in Table 7-4, the
registers are configured differently in non-DMA mode and DMA mode, and that the SPI slave data is output in
advance in DMA mode.
Table 7-4. Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave
Registers
SPI_CK_IDLE_EDGE
SPI_CK_I_EDGE
SPI_MISO_DELAY_MODE
SPI_MISO_DELAY_NUM
SPI_MOSI_DELAY_MODE
SPI_MOSI_DELAY_NUM
1. mode0 means CPOL=0, CPHA=0. When SPI is idle, the clock output is logic low; data changes on the
falling edge of the SPI clock and is sampled on the rising edge;
2. mode1 means CPOL=0, CPHA=1. When SPI is idle, the clock output is logic low; data changes on the
rising edge of the SPI clock and is sampled on the falling edge;
Espressif Systems
mode0
0
0
2(0)
0
0
0
/8. The master can derive other clock frequencies via frequency
apb
f =
spi
(SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1)
SPI_CLKCNT_N+1
–1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L. When the SPI_CLK_EQU_SYSCLK
2
7-3 and Table 7-4 show the clock polarity and phase as well as the corresponding
mode0
Non-DMA DMA
1 0
0 1
0 0
0 2
2 0
2 3
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mode1 mode2
0 1
1 1
1(0) 1(0)
0 0
0 0
0 0
/2, and the maximum input clock fre-
apb
f
apb
mode1 mode2
Non-DMA
1 0
1 1
2 0
0 0
0 1
0 2
mode3
1
0
2(0)
0
0
0
7.7 Register De-
mode3
DMA
1 0
0 0
0 1
2 0
0 0
3 0
ESP32 TRM (Version 5.2)