Espressif ESP32 Technical Reference Manual page 291

11 I2C Controller (I2C)
• DATA_Shifter which converts the byte data to an outgoing bitstream, or converts an incoming bitstream to
byte data. I2C_RX_LSB_FIRST and I2C_TX_LSB_FIRST can be used for configuring whether the LSB or
MSB is stored or transmitted first.
• SCL_Filter and SDA_Filter: Input noise filter for the I2C_Slave. The filter can be enabled or disabled by
configuring I2C_SCL_FILTER_EN and I2C_SDA_FILTER_EN. The filter can remove line glitches with pulse
width less than I2C_SCL_FILTER_THRES and I2C_SDA_FILTER_THRES ABP clock cycles.
11.3.3 I2C Bus Timing
Figure 11-3 is an I2C sequence chart. When the I2C controller works in master mode, SCL is an output signal. In
contrast, when the I2C controller works in slave mode, the SCL becomes an input signal. The values assigned
to I2C_SDA_HOLD_REG and I2C_SDA_SAMPLE_REG are still valid in slave mode. Users need to configure the
values of I2C_SDA_HOLD_TIME and I2C_SDA_SAMPLE_TIME, according to the host characteristics, for the I2C
slave to receive data properly. Table
configured to direct output mode. The settings determine the SCL output frequency f
I2C_SCL_FILTER_EN I2C_SCL_FILTER_THRES
0 Don't care
[0,2]
1
[3,7]
According to the I2C protocol, each transmission of data begins with a START condition and ends with a STOP
condition. Data is transmitted by one byte at a time, and each byte has an ACK bit. The receiver informs the
transmitter to continue transmission by pulling down SDA, which indicates an ACK. The receiver can also indicate
it wants to stop further transmission by pulling up the SDA line, thereby not indicating an ACK.
Figure 11-3 also shows the registers that can configure the START bit, STOP bit, SDA hold time, and SDA sample
time.
Notice: If the I2C pads are configured in open-drain mode, it will take longer for the signal lines to transition from
a low level to a high level. The transition duration is determined together by the pull-up resistor and capacitor.
The output frequency of SCL is relatively low in open-drain mode.
Espressif Systems
Figure 11-3. I2C Sequence Chart
11-1 shows available settings of SCL low and high level cycles when SCL is
Table 11-1. SCL Frequency Configuration
SCL_Low_Level_Cycles
I2C_SCL_LOW_PERIOD+1
f =
scl
SCL_Low_Level_Cycles + SCL_High_Level_Cycles
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SCL_High_Level_Cycles
I2C_SCL_HIGH_PERIOD+7
I2C_SCL_HIGH_PERIOD+8
I2C_SCL_HIGH_PERIOD+6+I2C_SCL_FILTER_THRES
80 MHz
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scl
ESP32 TRM (Version 5.2)