Espressif ESP32 Technical Reference Manual page 681

30 ULP Coprocessor (ULP)
30.8 Registers
30.8.1 SENS_ULP Address Space
The addresses in parenthesis besides register names are the register addresses relative to (the RTC base
address + 0x0800). The RTC base address is provided in Table
System and Memory. The absolute register addresses are listed in Section
Space.
Register 30.1. SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) (0x18+0x4*n)
31
SENS_ULP_CP_SLEEP_CYCn_REG ULP timer cycles setting n; the ULP coprocessor can select one
of such registers by using the SLEEP instruction. (R/W)
31
0 0 0 0 0 0 0
SENS_PC_INIT ULP PC entry address. (R/W)
SENS_ULP_CP_START_TOP Set this bit to start the ULP coprocessor; it is active only when
SENS_ULP_CP_FORCE_START_TOP = 1. (R/W)
SENS_ULP_CP_FORCE_START_TOP 1: ULP coprocessor is started by
SENS_ULP_CP_START_TOP; 0: ULP coprocessor is started by timer. (R/W)
Espressif Systems
Register 30.2. SENS_SAR_START_FORCE_REG (0x002c)
22 21
0 0 0 0 0 0 0 0
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1-6 Peripheral Address Mapping in Chapter
20
11 10 9
0 0 0 0 0 0 0 0
681
30.7.1 SENS_ULP Address
8 7
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
1
0
Reset
0
0
Reset