Espressif ESP32 Technical Reference Manual page 357

13 UART Controller (UART)
UHCI_DMA_IN_DSCR_BF1_REG
UHCI_DMA_OUT_DSCR_REG
UHCI_DMA_OUT_DSCR_BF0_REG
UHCI_DMA_OUT_DSCR_BF1_REG
Interrupt registers
UHCI_INT_RAW_REG
UHCI_INT_ST_REG
UHCI_INT_ENA_REG
UHCI_INT_CLR_REG
Espressif Systems
Current inlink descriptor,
third word
Current outlink descriptor,
first word
Current outlink descriptor,
second word
Current outlink descriptor,
third word
Raw interrupt status
Masked interrupt status
Interrupt enable bits
Interrupt clear bits
357
Submit Documentation Feedback
0x3FF54054 0x3FF4C054 RO
0x3FF54058 0x3FF4C058 RO
0x3FF5405C 0x3FF4C05C RO
0x3FF54060 0x3FF4C060 RO
0x3FF54004 0x3FF4C004 RO
0x3FF54008 0x3FF4C008 RO
0x3FF5400C 0x3FF4C00C R/W
0x3FF54010 0x3FF4C010 WO
ESP32 TRM (Version 5.2)