Espressif ESP32 Technical Reference Manual page 411

15 Remote Control Peripheral (RMT)
RMT_CH3CONF0_REG
RMT_CH3CONF1_REG
RMT_CH4CONF0_REG
RMT_CH4CONF1_REG
RMT_CH5CONF0_REG
RMT_CH5CONF1_REG
RMT_CH6CONF0_REG
RMT_CH6CONF1_REG
RMT_CH7CONF0_REG
RMT_CH7CONF1_REG
Interrupt registers
RMT_INT_RAW_REG
RMT_INT_ST_REG
RMT_INT_ENA_REG
RMT_INT_CLR_REG
Carrier wave duty cycle registers
RMT_CH0CARRIER_DUTY_REG
RMT_CH1CARRIER_DUTY_REG
RMT_CH2CARRIER_DUTY_REG
RMT_CH3CARRIER_DUTY_REG
RMT_CH4CARRIER_DUTY_REG
RMT_CH5CARRIER_DUTY_REG
RMT_CH6CARRIER_DUTY_REG
RMT_CH7CARRIER_DUTY_REG
Tx event configuration registers
RMT_CH0_TX_LIM_REG
RMT_CH1_TX_LIM_REG
RMT_CH2_TX_LIM_REG
RMT_CH3_TX_LIM_REG
RMT_CH4_TX_LIM_REG
RMT_CH5_TX_LIM_REG
RMT_CH6_TX_LIM_REG
RMT_CH7_TX_LIM_REG
Other registers
RMT_APB_CONF_REG
15.4 Registers
The addresses in parenthesis besides register names are the register addresses relative to the RMT base ad-
dress provided in Table 1-6
addresses are listed in Section
Espressif Systems
Channel 3 config register 0
Channel 3 config register 1
Channel 4 config register 0
Channel 4 config register 1
Channel 5 config register 0
Channel 5 config register 1
Channel 6 config register 0
Channel 6 config register 1
Channel 7 config register 0
Channel 7 config register 1
Raw interrupt status
Masked interrupt status
Interrupt enable bits
Interrupt clear bits
Channel 0 duty cycle configuration register
Channel 1 duty cycle configuration register
Channel 2 duty cycle configuration register
Channel 3 duty cycle configuration register
Channel 4 duty cycle configuration register
Channel 5 duty cycle configuration register
Channel 6 duty cycle configuration register
Channel 7 duty cycle configuration register
Channel 0 Tx event configuration register
Channel 1 Tx event configuration register
Channel 2 Tx event configuration register
Channel 3 Tx event configuration register
Channel 4 Tx event configuration register
Channel 5 Tx event configuration register
Channel 6 Tx event configuration register
Channel 7 Tx event configuration register
RMT-wide configuration register
Peripheral Address Mapping in Chapter
15.3 Register Summary.
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0x3FF56038 R/W
0x3FF5603C R/W
0x3FF56040 R/W
0x3FF56044 R/W
0x3FF56048 R/W
0x3FF5604C R/W
0x3FF56050 R/W
0x3FF56054 R/W
0x3FF56058 R/W
0x3FF5605C R/W
0x3FF560A0 RO
0x3FF560A4 RO
0x3FF560A8 R/W
0x3FF560AC WO
0x3FF560B0 R/W
0x3FF560B4 R/W
0x3FF560B8 R/W
0x3FF560BC R/W
0x3FF560C0 R/W
0x3FF560C4 R/W
0x3FF560C8 R/W
0x3FF560CC R/W
0x3FF560D0 R/W
0x3FF560D4 R/W
0x3FF560D8 R/W
0x3FF560DC R/W
0x3FF560E0 R/W
0x3FF560E4 R/W
0x3FF560E8 R/W
0x3FF560EC R/W
0x3FF560F0 R/W
Memory. The absolute register
ESP32 TRM (Version 5.2)