Espressif ESP32 Technical Reference Manual page 391

14 LED PWM Controller (LEDC)
14.2.2 Timers
... ...
Divider input
clock
...
Clock pulses
divided by A
Divider output
clock
The clock of each high-speed timer, LEDC_CLKx, has two clock sources: REF_TICK or APB_CLK. For more
information on the clock sources, please see Chapter
divider first. The division factor is specified by
number: the highest 10 bits represent the integer portion A, while the lowest eight bits contain the fractional
portion B. The effective division factor
The division factor ranges from 1 ∼ 1023.
When the fractional part B is not 0, the input and output clock of the divider is shown as in figure 14-3. Among
the 256 output clocks, B of them are divided by (A+1), whereas the remaining (256-B) are divided by A. Output
clocks divided by (A+1) are evenly distributed in the total 256 output clocks.
The output clock of the divider is the base clock for the counter which will count up to the value specified in
LEDC_HSTIMERx_DUTY_RES. An overflow interrupt will be generated once the counting value reaches
LEDC_HST IM ERx_DU T Y _RES
2
reset, suspend, and read the values of the counter by software.
The output signal of the timer is the 20-bit value generated by the counter. The cycle period of this signal
defines the frequency of the signals of any PWM channels connected to this timer.
The frequency of a PWM generator output signal, sig_outn, depends on the frequency of the timer's clock
source LEDC_CLKx, the division factor of the divider LEDC_CLK_DIVx, as well as the duty resolution (counter
width) LEDC_HSTIMERx_DUTY_RES:
Based on the formula above, the desired duty resolution can be calculated as follows:
LEDC_HSTIMERx_DUTY_RES = log
Table 14-1 lists the commonly-used frequencies and their corresponding resolutions.
Espressif Systems
... ... ...
Clock pulses divided
Clock pulses
Clock pulses
by (A+1)
divided by A divided by A
Figure 14-3. LED_PWM Divider
LEDC_CLK_DIV_NUM_HSTIMERx
LEDC_CLK_DIVx
LEDC_CLK_DIV
1, at which point the counter restarts counting from 0. It is also possible to
f =
sig_outn
LEDC_CLK_DIVx
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... ... ... ...
...
Clock pulses
Clock pulses divided
divided by A by (A+1) ...
B clock pulses divided
by (A+1)
...
256 output clock pulses
Reset And Clock. The input clock is divided down by a
is as follows:
B
x
= A +
256
f
LEDC_CLKx
· 2
LEDC_HSTIMERx_DUTY_RES
f
LEDC_CLKx
·
2
LEDC_CLK_DIVx
f
sig_outn
391
... ...
Clock pulses divided
Clock pulses
by (A+1)
divided by A
which contains a fixed point
ESP32 TRM (Version 5.2)