Espressif ESP32 Technical Reference Manual page 251

10 Ethernet Media Access Controller (MAC)
Name
EMACADDR1HIGH_REG
EMACADDR1LOW_REG
EMACADDR2HIGH_REG
EMACADDR2LOW_REG
EMACADDR3HIGH_REG
EMACADDR3LOW_REG
EMACADDR4HIGH_REG
EMACADDR4LOW_REG
EMACADDR5HIGH_REG
EMACADDR5LOW_REG
EMACADDR6HIGH_REG
EMACADDR6LOW_REG
EMACADDR7HIGH_REG
EMACADDR7LOW_REG
EMACWDOGTO_REG
Clock configuration registers
EMAC_EX_CLKOUT_CONF_REG
EMAC_EX_OSCCLK_CONF_REG
EMAC_EX_CLK_CTRL_REG
PHY type and SRAM configuration registers
EMAC_EX_PHYINF_CONF_REG
EMAC_PD_SEL_REG
10.10 Registers
The addresses in parenthesis besides register names are the register addresses relative to the EMAC base
address provided in Table
register addresses are listed in Section
Espressif Systems
Description
MAC address filtering and upper 16 bits
of the second 6-byte MAC address
Lower 32 bits of the second 6-byte
MAC address
MAC address filtering and upper 16 bits
of the third 6-byte MAC address
Lower 32 bits of the third 6-byte MAC
address
MAC address filtering and upper 16 bits
of the fourth 6-byte MAC address
Lower 32 bits of the fourth 6-byte MAC
address
MAC address filtering and upper 16 bits
of the fifth 6-byte MAC address
Lower 32 bits of the fifth 6-byte MAC
address
MAC address filtering and upper 16 bits
of the sixth 6-byte MAC address
Lower 32 bits of the sixth 6-byte MAC
address
MAC address filtering and upper 16 bits
of the seventh 6-byte MAC address
Lower 32 bits of the seventh 6-byte
MAC address
MAC address filtering and upper 16 bits
of the eighth 6-byte MAC address
Lower 32 bits of the eighth 6-byte MAC
address
Watchdog timeout control
RMII clock divider setting
RMII clock half and whole divider set-
tings
Clock enable and external / internal
clock selection
Selection of MII / RMII phy
Ethernet RAM power-down enable
1-6 Peripheral Address Mapping in Chapter
10.9 Register
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Address Access
0x3FF6A048 R/W
0x3FF6A04C R/W
0x3FF6A050 R/W
0x3FF6A054 R/W
0x3FF6A058 R/W
0x3FF6A05C R/W
0x3FF6A060 R/W
0x3FF6A064 R/W
0x3FF6A068 R/W
0x3FF6A06C R/W
0x3FF6A070 R/W
0x3FF6A074 R/W
0x3FF6A078 R/W
0x3FF6A07C R/W
0x3FF6A0DC R/W
0x3FF69800 R/W
0x3FF69804 R/W
0x3FF69808 R/W
0x3FF6980C R/W
0x3FF69810 R/W
Memory. The absolute
ESP32 TRM (Version 5.2)