Espressif ESP32 Technical Reference Manual page 132

7 SPI Controller (SPI)
3. mode2 means when CPOL=1, CPHA=0. When SPI is idle, the clock output is logic high; data changes on
the rising edge of the SPI clock and is sampled on the falling edge;
4. mode3 means when CPOL=1, CPHA=1. When SPI is idle, the clock output is logic high; data changes on
the falling edge of the SPI clock and is sampled on the rising edge.
7.4.2 GP-SPI Timing
The data signals of ESP32 GP-SPI can be mapped to physical pins either via IO_MUX or via IO_MUX and GPIO
matrix. Input signals will be delayed by two clk
signals will not be delayed.
When GP-SPI is used as master and the data signals are not received by the SPI controller via GPIO matrix, if GP-
SPI output clock frequency is clk
the clock polarity. If GP-SPI output clock frequency is not higher than clk
can be set to the corresponding value in Table
When GP-SPI is used in master mode and the data signals enter the SPI controller via the GPIO matrix:
1. If GP-SPI output clock frequency is clk
dummy phase should be enabled (SPI_USR_DUMMY = 1) for one clk
LELEN = 0) when configuring the clock polarity;
2. If GP-SPI output clock frequency is clk
configuring the clock polarity;
3. If GP-SPI output clock frequency is not higher than clk
to the corresponding value in Table
When GP-SPI is used in slave mode, the clock signal and the data signals should be routed to the SPI controller
via the same path, i.e., neither the clock signal nor the data signals passes through GPIO matrix, or both of
them pass through GPIO matrix. This is important in ensuring that the signals are not delayed by different time
periods before they reach the SPI hardware.
Assume that t , t and t
spi pre
delay time, respectively. Assume the SPI slave's main clock period is t
output is delayed by t :
v
• t < 3.5 ∗ t
, if CLK does not pass through GPIO matrix;
v apb
• t < 5.5 ∗ t
, if CLK passes through GPIO matrix.
v
apb
In DMA mode1 and mode3, SPI slave data output is delayed by the same period of time as in non-DMA mode.
However, for mode0 and mode2, SPI slave data is output earlier by t
• t 5.5 ∗ t
< (t /2
pre spi
• t 7.5 ∗ t
< (t /2
pre spi
Espressif Systems
apb
/2, register SPI_MISO_DELAY_MODE should be set to 0 when configuring
apb
7-3
/2, register SPI_MISO_DELAY_MODE should be set to 0 and the
apb
/4, register SPI_MISO_DELAY_MODE should be set to 0 when
apb
7-3 when configuring the clock polarity.
in Figure 7-4 denote SPI clock period, how far ahead data output is, and data output
v
), if CLK does not pass through GPIO matrix;
apb
), if CLK passes through GPIO matrix.
apb
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clock cycles when they pass through the matrix. Output
/4, register SPI_MISO_DELAY_MODE
apb
when configuring the clock polarity.
spi
/8, register SPI_MISO_DELAY_MODE can be set
apb
. For non-DMA mode0, SPI slave data
apb
:
pre
132
clock cycle (SPI_USR_DUMMY_CYC
ESP32 TRM (Version 5.2)