Espressif ESP32 Technical Reference Manual page 122

6 DMA Controller (DMA)
6 DMA Controller (DMA)
6.1 Overview
Direct Memory Access (DMA) is used for high-speed data transfer between peripherals and memory, as well as
from memory to memory. Data can be quickly moved with DMA without any CPU intervention, thus allowing for
more efficient use of the cores when processing data.
In the ESP32, 13 peripherals are capable of using DMA for data transfer, namely, UART0, UART1, UART2, SPI1,
SPI2, SPI3, I2S0, I2S1, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi.
6.2 Features
The DMA controllers in the ESP32 feature:
• AHB bus architecture
• Support for full-duplex and half-duplex data transfers
• Programmable data transfer length in bytes
• Support for 4-beat burst transfer
• 328 KB DMA address space
• All high-speed communication modules powered by DMA
6.3 Functional Description
All modules that require high-speed data transfer in bulk contain a DMA controller. DMA addressing uses the
same data bus as the CPU to read/write to the internal RAM.
Each DMA controller features different functions. However, the architecture of the DMA engine (DMA_ENGINE)
is the same in all DMA controllers.
6.3.1 DMA Engine Architecture
The DMA Engine accesses SRAM over the AHB BUS. In Figure 6-1, the RAM represents the internal SRAM banks
available on ESP32. Further details on the SRAM addressing range can be found in Chapter
Espressif Systems
Figure 6-1. DMA Engine Architecture
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