Espressif ESP32 Technical Reference Manual page 109

5 DPort Registers
31
0 0 0 0 0 0 0
DPORT_APP_CACHE_MMU_IA_CLR Clears APP cache MMU error flag. (R/W)
DPORT_APP_CMMU_PD Disables APP cache MMU. (R/W)
DPORT_APP_CACHE_MASK_OPSDRAM Disables access from PRO_CPU DRAM1 to APP cache.
1: Disable
0: Enable
(R/W)
DPORT_APP_CACHE_MASK_DROM0 Disables access from APP_CPU DROM0 to APP cache.
1: Disable
0: Enable
(R/W)
DPORT_APP_CACHE_MASK_DRAM1 Disables access from APP_CPU DRAM1 to APP cache.
1: Disable
0: Enable
(R/W)
DPORT_APP_CACHE_MASK_IROM0 Disables access from APP_CPU IROM0 to APP cache.
1: Disable
0: Enable
(R/W)
DPORT_APP_CACHE_MASK_IRAM1 Disables access from APP_CPU IRAM1 to APP cache.
1: Disable
0: Enable
(R/W)
DPORT_APP_CACHE_MASK_IRAM0 Disables access from APP_CPU IRAM0 to APP cache.
1: Disable
0: Enable
(R/W)
Espressif Systems
Register 5.13. DPORT_APP_CACHE_CTRL1_REG (0x05C)
0 0 0 0 0 0 0 0
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14 13 12 11
0 0 0 0 0 0 0 0 0
109
6 5 4 3 2 1 0
0 0 1 1 1 1 1 1
Reset
ESP32 TRM (Version 5.2)