Espressif ESP32 Technical Reference Manual page 247

10 Ethernet Media Access Controller (MAC)
Bits Name
[1] CE: CRC Error
Extended Status Available/
[0]
Rx MAC Address
Bits Name
[31] Ctrl
[30:29] Reserved
[28:16] Reserved
[15] RER: Receive End of Ring
RCH: Second Address
[14]
Chained
[13] Reserved
RBS1: Receive Buffer 1
[12:0]
Size
Espressif Systems
Description
When set, this bit indicates that a Cyclic Redundancy Check (CRC)
Error occurred on the received frame. This field is valid only when
the Last Descriptor (RDES0[8]) is set.
When the IP Checksum Offload (Type 2) is present, this bit, when
set, indicates that the extended status is available in descriptor
word 4 (RDES4). This is valid only when the Last Descriptor bit
(RDES0[8]) is set. This bit is invalid when Bit 30 is set.
When IP Checksum Offload (Type 2) is present, this bit is set even
when the IP Checksum Offload engine bypasses the processing
of the received frame. The bypassing may be because of a non-IP
frame or an IP frame with a non-TCP/UDP/ICMP payload.
When the IPC Full Offload is not selected, this bit indicates an
Rx MAC Address status. When set, this bit indicates that the Rx
MAC Address registers value (1 to 15) matched the frame's DA field.
When reset, this bit indicates that the Rx MAC Address Register 0
value matched the DA field.
Table 10-10. Receive Descriptor 1 (RDES1)
Description
When set, this bit prevents setting the Status Register's RI bit
(CSR5[6]) for the received frame that ends in the buffer indicated
by this descriptor. This, in turn, disables the assertion of the in-
terrupt to Host because of the RI for that frame.
Reserved
Reserved
When set, this bit indicates that the descriptor list reached its fi-
nal descriptor. The DMA returns to the base address of the list,
creating a Descriptor Ring.
When set, this bit indicates that the second address in the de-
scriptor is the Next Descriptor address rather than the second
buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a
"don't care" value. RDES1[15] takes precedence over RDES1[14].
Reserved
Indicates the first data buffer size in bytes. The buffer size must
be a multiple of 4, even if the value of RDES2 (buffer1 address
pointer) is not aligned to bus width. When the buffer size is not
a multiple of 4, the resulting behavior is undefined. If this field
is 0, the DMA ignores this buffer and uses Buffer 2 or the next
descriptor depending on the value of RCH (Bit[14]).
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