Espressif ESP32 Technical Reference Manual page 326

12 I2S Controller (I2S)
I2S_CONF_REG is set to 0, so that the I2S0 module works in LCD master receiving mode, and the I2S0 module
clock is configured such that the WS signal of I2S0 outputs an appropriate frequency. Then, the SYSCON_SAR
ADC_DATA_TO_I2S bit of register SYSCON_APB_SARADC_CTRL_REG is set to 1. Enable I2S to receive data after
configuring the relevant registers of SARADC. For details, please refer to Chapter
Signal Processing.
The I2S0 module should be configured to master transmitting mode when it connects to the on-chip DAC.
Figure 12-18 shows the signal connection between the I2S0 module and the DAC. The DAC's control module
regards I2S_CLK as the clock in this configuration. As shown in Figure 12-19, when the data bus inputs data to
the DAC's control module, the latter will input right-channel data to DAC1 module and left-channel data to DAC2
module. When using the I2S DMA module, 8 bits of data-to-be-transmitted are shifted to the left by 8 bits of
data-to-be-received into the DMA double-byte type of buffer.
The I2S_LCD_EN bit of register I2S_CONF2_REG should be set to 1, while I2S_RX_SHORT_SYNC, I2S_TX_SHORT
_SYNC, I2S_CONF_REG , I2S_RX_MSB_SHIFT and I2S_TX_MSB_SHIFT should all be reset to 0. The I2S_TX_
SLAVE_MOD bit of register I2S_CONF_REG should be set to 0, as well, when using the DAC mode of I2S0.
Select a suitable transmit mode according to the standards of transmitting a 16-bit digital data stream. Configure
the I2S0 module clock to output a suitable frequency for the I2S_CLK and the WS of I2S. Enable I2S0 to send
data after configuring the relevant DAC registers.
12.6 I2S Interrupts
12.6.1 FIFO Interrupts
• I2S_TX_HUNG_INT: Triggered when transmitting data is timed out.
• I2S_RX_HUNG_INT: Triggered when receiving data is timed out.
Espressif Systems
Figure 12-18. DAC Interface of I2S
Figure 12-19. Data Input by I2S DAC Interface
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