Espressif ESP32 Technical Reference Manual page 520

18 Timer Group (TIMG)
31
0 0 0 0 0 0 0
TIMGn_INT_WDT_INT_ST The masked interrupt status bit for the
(RO)
TIMGn_INT_T1_INT_ST The masked interrupt status bit for the
TIMGn_INT_T0_INT_ST The masked interrupt status bit for the
31
0 0 0 0 0 0 0
TIMGn_INT_WDT_INT_CLR Set this bit to clear the
TIMGn_INT_T1_INT_CLR Set this bit to clear the
TIMGn_INT_T0_INT_CLR Set this bit to clear the
Espressif Systems
Register 18.22. TIMGn_INT_ST_REG (0x00a0)
0 0 0 0 0 0 0 0
Register 18.23. TIMGn_INT_CLR_REG (0x00a4)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
TIMGn_INT_WDT_INT
TIMGn_INT_T1_INT
TIMGn_INT_T0_INT
0 0 0 0 0 0 0 0
TIMGn_INT_WDT_INT
TIMGn_INT_T1_INT interrupt. (WO)
TIMGn_INT_T0_INT
520
3 2 1
0 0 0 0 0 0 0 0
interrupt.
interrupt. (RO)
interrupt. (RO)
3 2 1
0 0 0 0 0 0 0 0
interrupt. (WO)
interrupt. (WO)
ESP32 TRM (Version 5.2)
0
0 Reset
0
0
Reset