Espressif ESP32 Technical Reference Manual page 66

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
Name
RTCIO_RTC_GPIO_STATUS_W1TC_REG
RTCIO_RTC_GPIO_IN_REG
RTCIO_RTC_GPIO_PIN0_REG
RTCIO_RTC_GPIO_PIN1_REG
RTCIO_RTC_GPIO_PIN2_REG
RTCIO_RTC_GPIO_PIN3_REG
RTCIO_RTC_GPIO_PIN4_REG
RTCIO_RTC_GPIO_PIN5_REG
RTCIO_RTC_GPIO_PIN6_REG
RTCIO_RTC_GPIO_PIN7_REG
RTCIO_RTC_GPIO_PIN8_REG
RTCIO_RTC_GPIO_PIN9_REG
RTCIO_RTC_GPIO_PIN10_REG
RTCIO_RTC_GPIO_PIN11_REG
RTCIO_RTC_GPIO_PIN12_REG
RTCIO_RTC_GPIO_PIN13_REG
RTCIO_RTC_GPIO_PIN14_REG
RTCIO_RTC_GPIO_PIN15_REG
RTCIO_RTC_GPIO_PIN16_REG
RTCIO_RTC_GPIO_PIN17_REG
RTCIO_DIG_PAD_HOLD_REG
GPIO RTC function configuration registers
RTCIO_SENSOR_PADS_REG
RTCIO_ADC_PAD_REG
RTCIO_PAD_DAC1_REG
RTCIO_PAD_DAC2_REG
RTCIO_XTAL_32K_PAD_REG
RTCIO_TOUCH_CFG_REG
RTCIO_TOUCH_PAD0_REG
...
RTCIO_TOUCH_PAD9_REG
RTCIO_EXT_WAKEUP0_REG
RTCIO_XTL_EXT_CTR_REG
RTCIO_SAR_I2C_IO_REG
4.13 Registers
4.13.1 GPIO Matrix Registers
The addresses in parenthesis besides register names are the register addresses relative to the GPIO base ad-
dress provided in Table 1-6
addresses are listed in Section
Espressif Systems
Description
RTC GPIO interrupt status bit clear register
RTC GPIO input register
RTC configuration for pin 0
RTC configuration for pin 1
RTC configuration for pin 2
RTC configuration for pin 3
RTC configuration for pin 4
RTC configuration for pin 5
RTC configuration for pin 6
RTC configuration for pin 7
RTC configuration for pin 8
RTC configuration for pin 9
RTC configuration for pin 10
RTC configuration for pin 11
RTC configuration for pin 12
RTC configuration for pin 13
RTC configuration for pin 14
RTC configuration for pin 15
RTC configuration for pin 16
RTC configuration for pin 17
RTC GPIO hold register
Sensor pads configuration register
ADC configuration register
DAC1 configuration register
DAC2 configuration register
32KHz crystal pads configuration register
Touch sensor configuration register
Touch pad configuration register
...
Touch pad configuration register
External wake up configuration register
Crystal power down enable GPIO source
RTC I2C pad selection
Peripheral Address Mapping in Chapter
4.12.1 GPIO Matrix Register
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Summary.
66
Address
0x3FF48420 WO
0x3FF48424
0x3FF48428 R/W
0x3FF4842C R/W
0x3FF48430 R/W
0x3FF48434 R/W
0x3FF48438 R/W
0x3FF4843C R/W
0x3FF48440 R/W
0x3FF48444
0x3FF48448
0x3FF4844C R/W
0x3FF48450 R/W
0x3FF48454 R/W
0x3FF48458 R/W
0x3FF4845C R/W
0x3FF48460 R/W
0x3FF48464 R/W
0x3FF48468 R/W
0x3FF4846C R/W
0x3FF48474
0x3FF4847C
0x3FF48480 R/W
0x3FF48484
0x3FF48488
0x3FF4848C R/W
0x3FF48490 R/W
0x3FF48494
0x3FF484B8 R/W
0x3FF484BC R/W
0x3FF484C0 R/W
0x3FF484C4 R/W
Memory. The absolute register
ESP32 TRM (Version 5.2)
Access
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W