Espressif ESP32 Technical Reference Manual page 497

16 Motor Control PWM (PWM)
31 30 29 28 27 26 25
0 0 0 0 0 0 0
INT_CAP2_INT_ST The masked status bit for the interrupt triggered by capture on channel 2. (RO)
INT_CAP1_INT_ST The masked status bit for the interrupt triggered by capture on channel 1. (RO)
INT_CAP0_INT_ST The masked status bit for the interrupt triggered by capture on channel 0. (RO)
INT_FH2_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action
on PWM2. (RO)
INT_FH1_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action
on PWM1. (RO)
INT_FH0_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action
on PWM0. (RO)
INT_FH2_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM2. (RO)
INT_FH1_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM1. (RO)
INT_FH0_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM0. (RO)
INT_OP2_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 2 TEB
event. (RO)
INT_OP1_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 1 TEB
event. (RO)
INT_OP0_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 0 TEB
event. (RO)
INT_OP2_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 2 TEA
event. (RO)
INT_OP1_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 1 TEA
event. (RO)
INT_OP0_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 0 TEA
event. (RO)
INT_FAULT2_CLR_INT_ST The masked status bit for the interrupt triggered when event_f2 ends.
(RO)
INT_FAULT1_CLR_INT_ST The masked status bit for the interrupt triggered when event_f1 ends.
(RO)
INT_FAULT0_CLR_INT_ST The masked status bit for the interrupt triggered when event_f0 ends.
(RO)
INT_FAULT2_INT_ST The masked status bit for the interrupt triggered when event_f2 starts. (RO)
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Espressif Systems
Register 16.71. INT_ST_PWM_REG (0x0118)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
497
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset