Espressif ESP32 Technical Reference Manual page 204

9 SD/MMC Host Controller
1. The Host sets up the element (DES0-DES3) for reception, and sets the OWN bit (DES0[31]).
2. The Host programs the read-data command in the CMD register in BIU.
3. Then, the Host programs the required level of the receive-threshold (RX_WMARK field in FIFOTH register).
4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMA enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.
5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can
be done.
6. The DMAC engine then waits for a DMA interface request (dw_dma_req) from BIU. This request will be
generated, based on the programmed receive-threshold value. For the last bytes of the data which cannot
be accessed using a burst, single transfers are performed on the AHB.
7. The DMAC fetches the data from FIFO and transfers them to the Host memory.
8. When data span across multiple descriptors, the DMAC will fetch the next descriptor and extend its op-
eration using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.
9. When data reception is complete, the status information is updated in the IDSTS register by setting
Receive-Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write-transaction to DES0.
9.10 SD/MMC Timing
Figure 9-9 shows the timing diagram for SD/MMC in high-speed (HS) mode. Table
quirements. These requirements are crucial for ensuring reliable and synchronized data communication in HS
mode.
CK
D, CMD
(output)
D, CMD
(input)
Symbol Parameter
t Clock Low Time
W (CKL)
t Clock High Time
W (CKH)
Espressif Systems
t
W(CKH)
t
OV
Figure 9-9. SD/MMC Timing in HS Mode
Table 9-6. SD/MMC Timing Requirements
Conditions
f
P P
f
P P
204
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t
W(CKL)
t
OH
t
t
ISU
IH
Min Typ
= 80 MHz 11.5 12.5
= 80 MHz 11.5 12.5
ESP32 TRM (Version 5.2)
9-6 lists the timing re-
Max Unit
— ns
— ns