Espressif ESP32 Technical Reference Manual page 494

16 Motor Control PWM (PWM)
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INT_TIMER0_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
(R/W)
INT_TIMER2_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
(R/W)
INT_TIMER1_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
(R/W)
INT_TIMER0_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
(R/W)
INT_TIMER2_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 2 stops.
(R/W)
INT_TIMER1_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 1 stops. (R/W)
INT_TIMER0_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 0 stops.
(R/W)
Espressif Systems
Register 16.69. INT_ENA_PWM_REG (0x0110)
494
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ESP32 TRM (Version 5.2)