Espressif ESP32 Technical Reference Manual page 241

10 Ethernet Media Access Controller (MAC)
Bits Name
CIC: Checksum Insertion
[23:22]
Control
[21] TER: Transmit End of Ring
TCH: Second Address
[20]
Chained
VLIC: VLAN Insertion
[19:18]
Control
[17] Reserved
Espressif Systems
Description
These bits control the checksum calculation and insertion. The
following list describes the bit encoding:
• 2'b00: Checksum insertion is disabled.
• 2'b01: Only IP header checksum calculation and insertion
are enabled.
• 2'b10: IP header checksum and payload checksum calcu-
lation and insertion are enabled, but pseudo-header check-
sum is not calculated in hardware.
• 2'b11: IP Header checksum and payload checksum calcula-
tion and insertion are enabled, and pseudo-header check-
sum is calculated in hardware.
This field is valid when the First Segment control bit (TDES0[28])
is set.
When set, this bit indicates that the descriptor list reached its fi-
nal descriptor. The DMA returns to the base address of the list,
creating a Descriptor Ring.
When set, this bit indicates that the second address in the de-
scriptor is the Next Descriptor address, rather than the second
buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a
"don't care" value. TDES0[21] takes precedence over TDES0[20].
This bit should be set to 1.
When set, these bits request the MAC to perform VLAN tagging or
untagging before transmitting the frames. If the frame is modified
for VLAN tags, the MAC automatically recalculates and replaces
the CRC bytes. The following list describes the values of these
bits:
• 2'b00: Do not add a VLAN tag.
• 2'b01: Remove the VLAN tag from the frames before trans-
mission. This option should be used only with the VLAN
frames.
• 2'b10: Insert a VLAN tag with the tag value programmed in
VLAN Tag Inclusion or Replacement Register.
• 2'b1: Replace the VLAN tag in frames with the Tag value pro-
grammed in VLAN Tag Inclusion or Replacement Register.
This option should be used only with the VLAN frames.
Reserved
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ESP32 TRM (Version 5.2)