Espressif ESP32 Technical Reference Manual page 174

8 SDIO Slave Controller
31 27 26
0x00 0 0
SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave sending linked list descriptor
error. (WO)
SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave receiving linked list descriptor
error. (WO)
SLC0INT_SLC0_RX_EOF_INT_CLR Interrupt clear bit for Slave sending operation completion. (WO)
SLC0INT_SLC0_RX_DONE_INT_CLR Interrupt clear bit for single buffer's sent interrupt, in Slave
sending mode. (WO)
SLC0INT_SLC0_TX_SUC_EOF_INT_CLR Interrupt clear bit for Slave receiving operation completion.
(WO)
SLC0INT_SLC0_TX_DONE_INT_CLR Interrupt clear bit for single buffer's full event, in Slave receiv-
ing mode. (WO)
SLC0INT_SLC0_TX_OVF_INT_CLR Set this bit to clear the Slave receiving overflow interrupt. (WO)
SLC0INT_SLC0_RX_UDF_INT_CLR Set this bit to clear the Slave sending underflow interrupt. (WO)
SLC0INT_SLC0_TX_START_INT_CLR Set this bit to clear the interrupt for Slave receiving operation
initialization. (WO)
SLC0INT_SLC0_RX_START_INT_CLR Set this bit to clear the interrupt for Slave sending operation
initialization. (WO)
SLC0INT_SLC_FRHOST_BIT7_INT_CLR Set this bit to clear the
terrupt. (WO)
SLC0INT_SLC_FRHOST_BIT6_INT_CLR Set this bit to clear the
interrupt. (WO)
SLC0INT_SLC_FRHOST_BIT5_INT_CLR Set this bit to clear the
interrupt. (WO)
SLC0INT_SLC_FRHOST_BIT4_INT_CLR Set this bit to clear the
interrupt. (WO)
Continued on the next page...
Espressif Systems
Register 8.5. SLC0INT_CLR_REG (0x10)
21 20 19 18 17
0 0 0 0 0 0 0 0
Submit Documentation Feedback
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
SLC0INT_SLC_FRHOST_BIT7_INT
SLC0INT_SLC_FRHOST_BIT6_INT
SLC0INT_SLC_FRHOST_BIT5_INT
SLC0INT_SLC_FRHOST_BIT4_INT
174
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0 Reset
in-