Espressif ESP32 Technical Reference Manual page 81

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
31
x x x x x x x
RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status.
etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT-
CIO_RTC_GPIO_PINn_REG. 1: corresponding interrupt; 0: no interrupt. (R/W)
Register 4.42. RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C)
31
x x x x x x x
RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 interrupt set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be set. (WO)
Register 4.43. RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020)
31
x x x x x x x
RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared. (WO)
Espressif Systems
Register 4.41. RTCIO_RTC_GPIO_STATUS_REG (0x0018)
x x x x x x x x
x x x x x x x x
x x x x x x x x
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14 13
x x x 0 0 0 0 0
Bit14 is GPIO[0], bit15 is GPIO[1],
14 13
x x x 0 0 0 0 0
14 13
x x x 0 0 0 0 0
81
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset
0
0
Reset
0
0 Reset