Espressif ESP32 Technical Reference Manual page 148

7 SPI Controller (SPI)
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SPI_SLV_WR_BUF_DONE The raw interrupt status bit for the
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
SPI_SLV_RD_BUF_DONE The raw interrupt status bit for the
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
31 27 26 25
0 0 0 0 0 0 1
SPI_SLV_STATUS_BITLEN It is only used in slave half-duplex mode to configure the length of the
master writing into the status register. (R/W)
SPI_SLV_STATUS_FAST_EN Reserved.
SPI_SLV_STATUS_READBACK Reserved.
SPI_SLV_RD_ADDR_BITLEN It indicates the address length in bits minus one for a slave-read op-
eration. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_WR_ADDR_BITLEN It indicates the address length in bits minus one for a slave-write op-
eration. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_WRSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for write-status
operations. It is only valid in slave half-duplex mode.(R/W)
SPI_SLV_RDSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for read-status op-
erations. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_WRBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for write-buffer
operations. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_RDBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for read-buffer op-
erations. It is only valid in slave half-duplex mode. (R/W)
Espressif Systems
Register 7.15. SPI_SLAVE_REG (0x38)
Register 7.16. SPI_SLAVE1_REG (0x3C)
24
0 0 0 0 0 0 0 0
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SPI_SLV_WR_BUF_INT
SPI_SLV_RD_BUF_INT
16 15 10 9
0 0x00
148
interrupt. It is
interrupt. It is
4 3 2 1 0
0x00 0 0 0 0 Reset
ESP32 TRM (Version 5.2)