Espressif ESP32 Technical Reference Manual page 219

9 SD/MMC Host Controller
31 30 28 27 26
0 0x0 0 x x
DMA_MULTIPLE_TRANSACTION_SIZE Burst size of multiple transaction, should be programmed
same as DMA controller multiple-transaction-size SRC/DEST_MSIZE. 000: 1-byte transfer; 001:
4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte
transfer; 110: 128-byte transfer; 111: 256-byte transfer. (R/W)
RX_WMARK FIFO threshold watermark level when receiving data to card.When FIFO data count
reaches greater than this number (FIFO_RX_WATERMARK), DMA/FIFO request is raised. During
end of packet, request is generated regardless of threshold programming in order to complete
any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled,
then interrupt is generated instead of DMA request.During end of packet, interrupt is not gen-
erated if threshold programming is larger than any remaining data. It is responsibility of host to
read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet,
even if remaining bytes are less than threshold, DMA request does single transfers to flush out
any remaining bytes before Data Transfer Done interrupt is set. (R/W)
TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count
is less than or equal to this number (FIFO_TX_WATERMARK), DMA/FIFO request is raised. If In-
terrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated,
regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR)
interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet,
on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not be-
fore FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA
mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles
until required bytes are transferred. (R/W)
Espressif Systems
Register 9.19. FIFOTH_REG (0x004C)
x x x x x x x x
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16 15 12 11
x 0 0 0 0
219
0
0x0000
Reset
ESP32 TRM (Version 5.2)