29 On-Chip Sensors and Analog Signal Processing
31
APB_SARADC_SAR1_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC1, one byte for each pat-
tern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation,
[23:20] pattern5_channel, etc. (R/W)
31
APB_SARADC_SAR1_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC1, one byte for each pat-
tern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation,
[23:20] pattern9_channel, etc. (R/W)
31
APB_SARADC_SAR1_PATT_TAB4_REG Pattern tables 12 - 15 for SAR ADC1, one byte for each pattern
table: [31:28] pattern12_channel, [27:26] pattern12_bit_width, [25:24] pattern12_attenuation,
[23:20] pattern13_channel, etc. (R/W)
31
APB_SARADC_SAR2_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC2, one byte for each pat-
tern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation,
[23:20] pattern1_channel, etc. (R/W)
Espressif Systems
Register 29.28. APB_SARADC_SAR1_PATT_TAB2_REG (0x20)
0x00F0F0F0F
Register 29.29. APB_SARADC_SAR1_PATT_TAB3_REG (0x24)
0x00F0F0F0F
Register 29.30. APB_SARADC_SAR1_PATT_TAB4_REG (0x28)
0x00F0F0F0F
Register 29.31. APB_SARADC_SAR2_PATT_TAB1_REG (0x2C)
0x00F0F0F0F
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ESP32 TRM (Version 5.2)
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